The present invention relates to fabrication of integrated circuits and, in particular, to fabrication of submicron MOS devices.
The structure and the various components, or features, of a metal oxide semiconductor (MOS) device such as a Field Effect Transistor (MOSFET) are generally well known. Such devices are generally formed having a source region and a drain region, of similar conductivity type, separated by a channel region, of a differing conductivity type, capped with a conductive gate. The gate to source voltage controls the passage of current through the channel region between the source and the drain regions. In a typical n-channel operation, a positive voltage is applied between the drain and the source with the source grounded to a reference potential. Due to the differing conductivity types of the channel region separating the source and the drain, usually no current flows between the source and drain. However, if a sufficiently large voltage is applied between the gate and source, the channel region will be turned on, thereby allowing current to flow between the source and the drain. The gate voltage required to induce the flow of current between the drain and the source is referred to as the threshold voltage.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high-density integrated circuit, features such as the gate conductor, source/drain regions, and interconnects to the junction must be made as small as possible. Many modern day processes employ features, which have less than 0.15 micron critical dimensions. As feature size decreases, the resulting transistor as well as the interconnect between transistors also decreases. Smaller transistors allow more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single and relatively small area. Further, smaller transistors typically have lower turn-on threshold voltages, faster switching speeds, and consume less power in their operation. These features in combination allow for higher speed integrated circuits to be constructed that have greater processing capabilities.
The benefits of high density can only be realized if advanced processing techniques are used. However, these techniques must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot in all instances offset the problems associated with small features or features arranged extremely close to one another. For example, as the channel length (distance between source and drain regions) decreases, short-channel effects (SCEs) generally occur, which can result in increased sub threshold leakage, and can become exaggerated when dimensions of the transistor and the channel region is decreased. Such a condition may be due to avalanche breakdown or punch through. Punch through occurs when the MOS transistor is biased in an off state with the gate and the source both at approximately zero volts with respect to ground, but with the drain at a voltage as high as 5 volts. Even though no flow of current is desired, drain current may still occur regardless of the zero gate voltage. This is due to the fact that under such conditions, the normal doping concentration of the channel region is not sufficient to prevent flow between the source and drain regions.
In order to eliminate punch through currents, the doping concentration in the substrate of the MOS device is raised. A so-called xe2x80x9cpunch through stopxe2x80x9d implant is used to locally raise the doping concentration of the MOS device substrate. Typically, the punch through stop implant is made as an angle implant over the active region of the MOS device. Unfortunately, the punch through stop implant also raises the doping concentration of the substrate in the source and drain region. As a consequence of the increased doping concentration, the source-drain junction capacitance is also increased.
Currently to overcome SCEs, punch through implants, also referred to as xe2x80x9cpocket implants,xe2x80x9d are substituted with buried dielectric plugs, which isolate vertical sidewalls of the deep regions from the channel regions except for their uppermost part-inversion layer. This prevents the transistors from the bulk punch through without reducing the depth of highly doped regions and without increasing the channel doping that has a detrimental effect for current driving capability and junction capacitance. The pocket implants may be reduced or even withdrawn. In addition, the dielectric plugs reduce junction capacitance and cut down the path of punch through current in the channel region. This technique is described in detail in xe2x80x9cDielectric Pockets-A New Concept of the Junctions for Deca-Manometric CMOS Devices,xe2x80x9d IEEE Transactions on Electron Devices, Vol. 48, No. 8, August 2001.
However, the above-described process can require extreme fine-tuning of process control parameters during dry etching to form the dielectric plugs. This requirement of a fine control on the process parameters during fabrication of the dielectric plugs can result in uncontrolled position, height, and thickness of the formed dielectric plugs, which are critical to reducing SCEs. This can also result in uncontrolled channel length and not connecting to source/drain regions to low doping drain (LDD) regions, also referred to as xe2x80x9cSource/Drain extensions.xe2x80x9d In addition, Silicon/Nitride used in forming the dielectric plugs during the dry etching process, can result in having a poor bonding with the silicon substrate, which can further result in traps and junction leakage.
Thus, there is a need in the art for a technique to form dielectric plugs that overcomes the shortcoming of the above-described process. Further, there is a need for a feasible technique to form closely controlled dielectric plugs to reduce SCEs. In addition, there is a need for a technique to form these dielectric plugs without substantially increasing source-drain junction capacitance, and which minimizes SCEs.
The present invention provides an advanced technique for fabricating a MOSFET including a dielectric plug to reduce short channel effects without increasing source-drain junction capacitance. Further, the technique provides a fabrication process to form a self-aligned dielectric plug having good control on the position, size, and thickness of the formed dielectric plug, which are critical to reducing the SCEs. In addition, the technique provides a more robust, less complex, and more cost effective process to fabricate the device including the dielectric plug.
In one embodiment, the MOSFET is fabricated by forming a pair of low doping drain (LDD) regions substantially adjacent to a gate electrode stack on a substrate including a protective cap layer over the gate stack and a first spacer layer around the gate stack. A first layer is then removed in the substrate by etching the substrate to expose a side silicon in the LLD regions and substantially under the first spacer layer and to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions. A second spacer is then formed over the first spacer layer such that the formed second spacer layer substantially extends from the exposed source and drain regions. A second layer is then removed in the substrate around and under the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions. The exposed substrate extends the formed side silicon in the LDD regions further into the substrate to form a sidewall and a recess for the source and drain regions. An oxide layer is then formed over the exposed substrate in the formed source and drain recesses and sidewalls such that the formed second spacer layer and the formed oxide layer substantially close the exposed LDD regions. The second spacer layer is then removed by selective etching to expose the closed LDD regions. The formed oxide layer is then substantially removed from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the LDD regions and around the sidewalls of the source and drain regions to form a dielectric plug and a channel region between the source and drain regions to reduce short channel effects between source and drain regions. Epitaxial silicon material is then deposited in the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.
In another embodiment, the MOSFET is fabricated by forming a protective cap layer over a gate electrode stack disposed on a substrate over an active region surrounded by an isolation region. A first spacer layer is then formed around the gate electrode stack such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack. A first layer is then removed in the substrate to expose the substrate to form source and drain regions such that the formed source and drain regions are disposed substantially adjacent to the gate electrode stack and apart from each other at opposite sides of the gate electrode stack. A second spacer layer is then formed over the formed first spacer layer such that the formed second spacer layer substantially extends from the exposed source and drain regions. A second layer is then removed from the substrate around the formed second spacer layer and source and drain regions to further expose the substrate to form a sidewall in the substrate and a recess for the source and drain regions. An oxide layer is then formed over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer and the oxide layer substantially close the sidewalls. The second spacer layer is then removed by selective etching to expose the first spacer layer. The formed oxide layer is then substantially removed from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer around the sidewalls of the source and drain regions to form a dielectric plug and a channel region between the source and drain regions. Epitaxial silicon material is then deposited in the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions. A portion of the first spacer layer around the source and drain regions is then etched back to expose silicon regions for LDD implantation, such that the exposed regions are disposed substantially adjacent to the gate electrode stack and the source and drain regions. The exposed regions are implanted with a dopant to form a LDD region to connect the channel region with the source and drain regions. A third spacer layer is then formed over the gate electrode stack.
Additional advantages and features of the present invention will be more apparent from the detailed description and accompanying drawings, which illustrate preferred embodiments of the invention.